KVM: riscv: Fix NACL hfence entry update order
In the Linux kernel, the following vulnerability has been resolved: KVM: riscv: Fix NACL hfence entry update order The SBI v3.0 specification (section 15.1.2) requires a nested HFENCE entry to be populated as follows: 1) find an unused entry with Config.Pending == 0 2) update the Page_Number and Page_Count words 3) update the Config word with Config.Pending set __kvm_riscv_nacl_hfence() writes the Config word first, so the SBI implementation (or NACL hardware) can observe a pending entry with pnum/pcount values left over from the previous use of that entry, resulting in incorrect TLB flush ranges. Write pnum and pcount first and the Config word last. Since the consumer is an external agent on coherent shared memory, use WRITE_ONCE() to stop the compiler from reordering the stores and smp_wmb() to make the parameter words globally visible before the Pending bit is set.
- Products
- Kernel
- Affected versions
- Not specified
- Fixed versions
- 6.18.55, 7.2.9
- CVEs
- CVE-2026-98639
- Confirmed fixed CVEs
- Not specified
- Updated in this feed
- 3 Nov 2026, 23:30 UTC · Revision 1
Source evidence
KVM: riscv: Fix NACL hfence entry update order
core-osv · Original sourcePublished 18 Oct 2026, 15:20 UTC
In the Linux kernel, the following vulnerability has been resolved: KVM: riscv: Fix NACL hfence entry update order The SBI v3.0 specification (section 15.1.2) requires a nested HFENCE entry to be populated as follows: 1) find an unused entry with Config.Pending == 0 2) update the Page_Number and Page_Count words 3) update the Config word with Config.Pending set __kvm_riscv_nacl_hfence() writes the Config word first, so the SBI implementation (or NACL hardware) can observe a pending entry with pnum/pcount values left over from the previous use of that entry, resulting in incorrect TLB flush ranges. Write pnum and pcount first and the Config word last. Since the consumer is an external agent on coherent shared memory, use WRITE_ONCE() to stop the compiler from reordering the stores and smp_wmb() to make the parameter words globally visible before the Pending bit is set.
osv:CVE-2026-98639
Kernel
Fixed versions: 6.18.55, 7.2.9
Complete source record
{
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"url": "https://osv.dev/vulnerability/CVE-2026-98639",
"method": "structured",
"payload": {
"kind": "advisory",
"title": "KVM: riscv: Fix NACL hfence entry update order",
"summary": "In the Linux kernel, the following vulnerability has been resolved: KVM: riscv: Fix NACL hfence entry update order The SBI v3.0 specification (section 15.1.2) requires a nested HFENCE entry to be populated as follows: 1) find an unused entry with Config.Pending == 0 2) update the Page_Number and Page_Count words 3) update the Config word with Config.Pending set __kvm_riscv_nacl_hfence() writes the Config word first, so the SBI implementation (or NACL hardware) can observe a pending entry with pnum/pcount values left over from the previous use of that entry, resulting in incorrect TLB flush ranges. Write pnum and pcount first and the Config word last. Since the consumer is an external agent on coherent shared memory, use WRITE_ONCE() to stop the compiler from reordering the stores and smp_wmb() to make the parameter words globally visible before the Pending bit is set.",
"evidence": "osv:CVE-2026-98639",
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"modified": "2026-10-28T02:30:32.163710166Z",
"provider": "osv",
"references": [
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"https://git.kernel.org/stable/c/b3d346838ec65fac7fd83f5dbcedd13cadfffddb",
"https://git.kernel.org/stable/c/d6de766d8d26d71b714f548192099112def50a9c",
"https://github.com/CVEProject/cvelistV5/tree/main/cves/2026/98xxx/CVE-2026-98639.json",
"https://nvd.nist.gov/vuln/detail/CVE-2026-98639",
"https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git"
],
"provider_metadata": {
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"security_relevant": true,
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"source_id": "core-osv",
"document_id": 499256,
"published_at": "2026-10-18T15:20:10.591+00:00"
}